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笔试题（physical design）
physical design
1.before tape-out,which routine check should be performed for your layout database in 0.18 um process?
a.drc
b.lvs
c.drc&antenna
e.simulation
2.how to fix antenna effect?
a.make the wire wider and shorter
b.change lower metal to upper metal
c.connect with diode of metal and diffusion
d.change upper metal to lower metal
e.b&c
3.please expain lvs
a.logic versus schematic
b.layout versus schematic
c.layout via synthesis
d.logic via synthesis
4.how to control clock skew?
a.get balanced clock tree
b.decrease the fanout
c.add clock buffer evenly
d.decrease clock latency
5.how to avoid hold_time violation?
a.lower the clock speed
b.the clock arrive later
c.the clock arrive earlier
d.the data arrive later
e.the data arrive earlier
6.what kinds of factors reflect good floor plan?
a.easy routing
b.easy timing met
c.enough power supply
d.a&b
e.a&b&c
7.what cause cell delay?
a.input-pin transition time
b.output-pin capacitance.
c.output-pin resistance
d.a&b
e.b&c
8.why need i/o pads for each chip?
a.esd protection
b.voltage level shift
c.latch-up prevention
d.a&c
e.a&b&c
9.which one is worse-case in 0.18um process?
1.1.8v,25c
2.1.98v,125c
3.1.62v,-40c
4.1.62v,125c
5.1.98v,-40c
10.if power plan is not good,what’ll happen to the chip?
a.hot-spot
b.voltage drop
c.timing not met
d.routing is tough
e.all of above
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